Clock recovery is often employed in synchronous digital systems. For example, clock recovery circuits and methods may be employed where data and clock signals are multiplexed through shared channels, where clock signals are transmitted over noisy channels, where data is transmitted without an accompanying clock signal, and/or the like. In these and other applications, clock recovery circuits and methods may be employed, for example, to recover bit clock signals, to recover frame synchronization signals, or to generate local oscillator (LO) signals.
Non-idealities such as channel noise, channel delays, electromagnetic interference, circuit delays, and/or the like, may adversely affect the recovery of clock signals. These and other non-idealities may cause glitches, jitter, noise, and/or the like, to be incorporated into the recovered clock signals and may decrease system performance. For example, non-idealities may increase the bit error rate (BER) in digital communications, may make it difficult for clock recovery circuit to lock onto a received clock, and/or the like. In certain applications, it may be beneficial to reduce the detrimental effects of these non-idealities.